An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS

A team of researchers has published a paper detailing a specialized hardware design to accelerate a key part of the JPEG XS image compression standard. The work focuses on the Intra Pattern Copy (IPC) tool, which reduces spatial redundancy in screen content by finding optimal prediction references, a process known as displacement vector (DV) search. This search is notoriously compute-heavy, hindering real-time deployment. The researchers' solution is a pipelined architecture for Field-Programmable Gate Arrays (FPGAs) that uses optimized memory organization to leverage data reuse patterns inherent to the IPC algorithm.

Experimental results demonstrate the design's efficiency, processing 38.3 million pixels per second while drawing a mere 277 milliwatts of power. This performance makes the DV search module feasible for practical hardware implementation. The breakthrough is significant for the JPEG XS ecosystem, a standard built for low-latency and low-complexity coding. It provides a concrete path toward deploying advanced compression in latency-sensitive fields like professional live video production, cloud gaming, and wireless display systems, and serves as a promising blueprint for future Application-Specific Integrated Circuit (ASIC) development.