Algorithm-hardware co-design of neuromorphic networks with dual memory pathways
Brain-inspired dual memory pathway slashes parameters by 60% while boosting energy efficiency 5x.
A team of researchers from UCL, ETH Zurich, and the University of Cambridge has published a groundbreaking paper on algorithm-hardware co-design for neuromorphic networks. Their dual memory pathway (DMP) architecture addresses a core limitation of spiking neural networks (SNNs): maintaining task-relevant context over long timescales while respecting tight energy and memory budgets. Inspired by the cortical fast-slow organization in the brain, each layer in the DMP network maintains a compact low-dimensional state that summarizes recent activity and modulates spiking dynamics. This explicit memory stabilizes learning while preserving event-driven sparsity, resulting in competitive accuracy on long-sequence benchmarks with 40–60% fewer parameters than equivalent state-of-the-art SNNs.
On the hardware side, the team designed a near-memory-compute architecture that fully leverages the DMP's advantages by retaining its compact shared state while optimizing dataflow across heterogeneous sparse-spike and dense-memory pathways. Experimental results demonstrate more than a 4x increase in throughput and over a 5x improvement in energy efficiency compared to state-of-the-art implementations. This co-design establishes a scalable framework for real-time neuromorphic computation and learning, bringing autonomous AI closer to energy-efficient edge deployment.
- Dual memory pathway (DMP) architecture mimics the brain's fast-slow neural dynamics to handle long-term context.
- Achieves 40–60% fewer parameters than state-of-the-art spiking neural networks on long-sequence benchmarks.
- Near-memory-compute hardware implementation yields 4x higher throughput and 5x better energy efficiency.
Why It Matters
Paves the way for energy-efficient, real-time neuromorphic computing in edge devices, robotics, and IoT sensors.