New Neural CPU Makes AI Execution Interpretable and Traceable

In a new 63-page paper, researcher Jose Luis Lima de Jesus Silva presents a symbolic neural CPU designed to make neural network program execution fully interpretable. Instead of treating neural computation as a black box, this architecture uses a trace-supervised, factorized learned execution model with explicit components: a recurrent controller, an operation router that selects from a fixed bank of differentiable arithmetic-logic units, and destination-masked register writeback. At every step, the model exposes the selected operation, source and destination registers, register trajectory, memory signals, and writeback semantics. On the principal 16-wide benchmark, the non-quantized executor reproduces reference execution exactly, while the 8-bit quantization-simulated executor preserves the symbolic operation path through programs of up to 1,000 instructions. A key insight is that residual numerical drift observed in previous work disappears when the same execution is evaluated against a matched fixed-point replay, proving the drift stems from a mismatch between continuous and low-precision reference semantics rather than execution failure.

The paper also compares recurrent, Transformer, temporal-convolution, temporal graph-inspired, and state-space controllers, showing that operation-gate supervision is critical for an inspectable execution path. Additional extensions include a ValueMemory interface, hybrid adaptive leaky integrate-and-fire controllers, and candidate-constrained symbolic control trained via behavior cloning and actor-critic reinforcement learning. The work even establishes a bridge to RV32I base-integer semantics. While hidden-opcode memory-pressure tasks reveal remaining limits in delayed state use and temporal binding, the overall framework demonstrates a viable path toward verifiable, low-precision neural execution. With 23 figures and supplementary information, this research could help build trust in AI systems that need to execute algorithmic logic under hardware constraints.