Pipelined FPGA p-computer accelerates probabilistic computing by 10x

Probabilistic Ising machines (PIMs) offer a hardware-friendly approach to combinatorial optimization, but digital implementations typically struggle with dense problems due to memory bandwidth bottlenecks. In a paper on arXiv (2607.21077), Deborah Volpe and colleagues present a resource-efficient pipelined Field-Programmable Gate Array architecture that overcomes these limitations. By combining a deeply pipelined probabilistic bit update path with over 20 stages and a bandwidth-aware on-chip memory organization for coupling and bias matrices, the design overlaps spin evaluation and local-field updates, enabling high throughput for fully-connected PIMs.

The architecture supports 512 p-bits with 16-bit fixed-point coefficients, and up to 1024 or 2048 p-bits with 10-bit and 2-bit coefficients respectively, operating at up to 300 MHz. At a fixed degree of parallelization, it delivers an order-of-magnitude higher update rate than an optimized non-pipelined baseline, while improving the time-area trade-off for dense workloads. Validation on portfolio optimization and low-density parity-check decoding shows close agreement with software references and substantial reductions in time-to-solution. This work establishes pipelining as an effective route to scalable digital probabilistic computing for dense optimization problems.