New VPD framework hits 87.6% efficiency for HPC power delivery
Cut power loss by 14% with GaN switches and stacked voltage conversion.
Power delivery remains a critical bottleneck in high-performance computing, with existing vertical power delivery (VPD) solutions wasting over 30% of input energy as heat before reaching on-chip loads. A team led by Sriharini Krishnakumar (arXiv, June 2026) introduces a comprehensive end-to-end design framework that dramatically improves efficiency. Their distributed VPD (DVPD) architecture uses GaN power switches embedded in the substrate, paired with arrays of unit inductors and capacitors optimized for HPC workloads.
By exploring multi-stage conversion schemes (48V-to-1V, 48V-to-24V-to-1V, and 48V-to-12V-to-1V), the framework achieves 84% system-wide efficiency with only 54% of the area beneath the load system. Expanding area utilization to 75% pushes efficiency to 87.6% across a 1–50 kW range. Steady-state voltage drops peak at just 2.7% and transient drops at 9% (without decoupling capacitors), proving DVPD viable for future wafer-scale HPC platforms. This replaces computationally prohibitive simulations with analytical models, enabling faster design exploration for next-generation chips.
- GaN power switches embedded in substrate enable 87.6% efficiency at 75% area usage.
- Multi-stage conversion (48V→1V) reduces power loss by 14 percentage points vs. existing VPD.
- Voltage drops stay under 2.7% steady-state and 9% transient across 1–50 kW loads.
Why It Matters
This framework could slash data center cooling costs and power budgets for future AI and HPC clusters.